1. Field of the Invention
This invention relates to a refresh operation control circuit for a semiconductor device. In particular, the invention relates to a refresh operation control circuit that manages and controls the timing of normal memory operations and refresh operations in a semiconductor memory capable of carrying out a refresh operation in the idle time of normal memory operation.
2. Description of the Related Art
A semiconductor memory which needs a refresh operation is a type of RAM (random access memory) in which the memory cells consist, for example, of a transistor and a capacitor. Virtual static RAMs are constructed such that the normal read operation and refresh operation are conducted by time sharing in the same access cycle, so that the user is not aware of the refresh operation (the refresh operation is invisible to the user). These RAMs are proposed in Japanese Patent Applications No. Sho. 59-163508 and No. Sho. 59-111894 of the same assignee. FIG. 1 shows an example of the construction of the memory cell core region that constitutes the major part of such a RAM. FIG. 2 shows an example of the timing chart of its operation. The characteristic feature of such a RAM is that the selected word lines of a memory cell array 51 and sense amplifiers 52 are respectively pulse-driven. Thus the data sensed by a sense amplifier by the normal read operation is transmitted to a buffer register 54 by a column decoder 53, where it is temporarily stored, and then read out to an input/output buffer 55. Since the electrical connection of sense amplifiers 52 and buffer registers 54 is switched with a prescribed timing, the refresh operation can be conducted during the idle time of normal memory operation. Specifically, a word line WL1 corresponding to the address specified by an address (ADD) signal and chip enable bar (CE) signal is opened for a certain period. During this period sense amplifiers 52 are operated in response to a sense amplifier enable (SAE) signal to sense and amplify data from memory cell array 51. This data is then re-written into the memory cells from which it was read. After this, a column decoder 53 is operated by a column decoder enable (CDE) signal. Under the control of its output the output of sense amplifier 52 is transmitted to buffer register 54. In response to a buffer register enable (BRE) signal, data is stored in buffer register 54. This data is output through an input/output buffer 55 from an output pin (not shown) as output data OUT. During the period until this data is output, the CDE and SAE signals are disabled, so the bit lines of memory cell array 51 can be accessed. The refresh address signal now causes refresh word line RWL (connected to the memory cell being refreshed) to be open for a certain time. This refresh word line RWL is separate from word line WL1. During this refresh operation, the CDE signal is still disabled, so the sense amplifier output cannot be read. Next, when the CE signal is enabled, the series of operations from selection of the word line (e.g. selection of WL2) by the address signal up to the refresh operation are performed in the same way as described above.
It should be noted that, although, in the timing of the above operations, the refresh operation took place after the read data was determined by the read operation, this is not essential, and it is possible to carry out the refresh operation before the normal read operation, during address decoding. Furthermore, although in the above operation example, the normal memory operation and refresh operation were performed by time sharing during a single access cycle, it is not essential to carry out the refresh operation every cycle. Normal memory operation and refresh operation can be performed by time sharing, as described above, in just those cycles in which refreshing is needed.
Thus a refresh timing control circuit is needed to manage and control the timing of refresh such that refresh operation is automatically carried out during the idle time of normal memory operation, as described above. Realization of a simple practical circuit to achieve this was required.